From seir, 5 Years ago, written in VHDL.
  1. -- The following code spawns a warning "Case choice must be a locally
  2. -- static expression" on lines 26, 30 and 34. How can I use generics
  3. -- for case ranges?
  4.  
  5.  
  6. entity spi_master is
  7.     generic (
  8.         N : positive := 32;
  9.         PREFETCH : positive := 3
  10.     );
  11.     port (
  12.         ...
  13.     );
  14. end spi_master;
  15.  
  16. architecture rtl of spi_master is
  17.     signal state_next : natural range N+1 downto 0 := 0;
  18.     signal state_reg : natural range N+1 downto 0 := 0;
  19.         ...
  20. begin
  21.     core_combi_proc : process (state_reg, ...) is
  22.     begin
  23.         state_next <= state_reg;
  24.         case state_reg is
  25.  
  26.             when (N) =>
  27.                 -- do stuff
  28.                 state_next <= state_reg - 1;
  29.  
  30.             when (N-1) downto (PREFETCH+3) =>
  31.                 -- do stuff
  32.                 state_next <= state_reg - 1;
  33.  
  34.             when (PREFETCH+2) downto 2 =>
  35.                 -- do stuff
  36.                 state_next <= state_reg - 1;
  37.  
  38.             when 1 =>
  39.                 -- do stuff
  40.                 state_next <= state_reg - 1;
  41.  
  42.             when 0 =>
  43.                 -- do stuff
  44.                 state_next <= N;
  45.  
  46.             when others =>
  47.                 state_next <= 0;
  48.         end case;
  49.     end process core_combi_proc;
  50.        
  51.         ...
  52. end architecture rtl;