RSFF.vhdl

-- Florian Bruhin

-- Bildungszentrum Uster

-- 22.05.2012

-- RSFF.vhdl - RS-Flipflop

library ieee;

use ieee.std_logic_1164.all;

entity RSFF is

port (

nSet, nRes: in std_logic;

Q, nQ: out std_logic

);

end entity;

architecture RSFF_behave of RSFF is

signal hQ, hnQ: std_logic;

begin

hQ <= (nSet nand hnQ);

hnQ <= (nRes nand hQ);

Q <= hQ;

nQ <= hnQ;

-- .---.

-- | |

-- nSet --+-| & |o-+----- Q

-- +-| | |

-- | '---' /

-- \ /

-- \ / hQ

-- \ /

-- X

-- / \

-- / \ hnQ

-- / \

-- | .---. \

-- +-| | |

-- nRes --+-| & |o-+----- nQ

-- | |

-- '---'

end architecture;

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